The present invention relates to transistor-level static performance analysis SPA methods. SPA is a method of bounding the performance of an integrated circuit (IC) design, prior to actually creating the IC in silicon. This is done by postulating worst case or best case performance at every signal flow juncture, for worst case or best case bounds, respectively. One particularly important type of SPA is static timing analysis (STA), in which timing performance is bounded. In STA, both best and worst case bounds are critical for insuring that there will be no timing mismatches, internal and external to the chip. Another technique, known as dynamic timing analysis, is the process of simulating circuit performance for a particular input set or vector. Unfortunately, for large circuits this technique becomes impractical due to the huge number simulation runs, each with a different input vector, which would have to be performed to gain a good confidence level that a worst case input vector had been identified. Because of its great importance, much of the discussion in this application is presented in terms of STA, although in some cases it could be generalized to include other types of performance. It may be noted that SPA also includes statistical analysis, that is analysis which does not presume a best or worst case performance for every device forming a part of the overall circuit, but which presumes a variation in device performance and arrives at a statistical distribution of IC performance results.
It is common to design an IC at the cell-level, using cells such as logic gates and flip-flops as the basic building blocks. In complementary metal oxide semiconductor (CMOS) circuitry, which is by far the most popular form of integrated circuitry, the distinction between a cell and a transistor is particularly clear. CMOS circuitry is made up of complementing negative doped metal oxide semiconductor (NMOS) and positive doped metal oxide semiconductor (PMOS). In CMOS even the simplest functional unit (that is, “cell”), such as an inverter, must include two complementary transistors. Because of the general tendency to design at the cell level; the most common STA tools are cell level tools, a leading example being Synopsis PrimeTime®. To use this type of tool, the delay information for each type of cell is pre-computed and subsequently used for performing STA on the circuit using a cell-level STA engine. In some situations, however, it is still necessary, in order to meet tight performance requirements, to design custom circuits and/or portions of an IC at the transistor-level. Because it is more unusual to design circuits at the transistor level, the tool suite available for performing STA at the transistor level is less robust than at the cell-level. Although at least one transistor-level STA tool does exist, it is less widely available than the cell-level timing tools. Accordingly, it would be a great benefit to IC designers, if there was some way to use cell-level STA tools to analyze a circuit designed at the transistor-level.